1. Field of the Invention
The technical field relates to an error amplifier applicable to a power supply circuit (switching regulator) or the like.
2. Description of the Related Art
FIG. 4 shows an example of the configuration of a power supply circuit. The power supply circuit includes an error amplifier 40, an oscillator 50 which generates a triangle wave, a PWM (pulse width modulation) comparator 60, an inductor L1, a transistor Q6, a diode D1, a capacitor C3, and resistors R6 and R7.
The error amplifier 40 is an important component to determine the frequency response of a feedback circuit in a power supply circuit. An input voltage Vin is input to an inverting input terminal of the error amplifier 40, and a reference voltage Vref is input to a non-inverting input terminal of the error amplifier 40.
The oscillator 50 is a circuit which generates a triangle wave Vosc necessary for generating a PWM signal.
An output signal Verr of the error amplifier 40 is input to the inverting input terminal of the PWM comparator 60, and the triangle wave Vosc generated by the oscillator 50 is input to the non-inverting input terminal of the PWM comparator 60.
The PWM comparator 60 compares the output signal Verr of the error amplifier 40 to the triangle wave Vosc When the signal level of the triangle wave Vosc is higher than that of the output signal Verr of the error amplifier 40, an H (high-level) signal is output as a PWM signal to the transistor Q6. On the other hand, when the signal level of the triangle wave Vosc is lower than that of the output signal Verr of the error amplifier 40, an L (low-level) signal is output as a PWM signal to the transistor Q6.
One of the source and drain of the transistor Q6 is connected to one terminal of the inductor L1 and the anode of the diode D1. The other one of the source and drain of the transistor Q6 is connected to a reference potential (GND).
The other terminal of the inductor L1 is connected to a power input terminal 65.
The cathode of the diode D1 is connected to an output terminal 70. The capacitor C3 is connected in parallel with a series circuit of the resistors R6 and R7, between the output terminal 70 and GND. The voltage of a connection point between the resistors R6 and R7 is input as a feedback voltage Vfb to the non-inverting input terminal of the error amplifier 40.
FIG. 3 shows an example of the configuration of a conventional error amplifier. A resistor R4 is connected between an input terminal 11 and an inverting input terminal of an operational amplifier 16. Moreover, a resistor R5 and a capacitor C2 are connected between an output terminal 12 and the inverting input terminal.
A transfer function representing a relation between an input signal and an output signal in this error amplifier is expressed by FORMULA 1.
                              V          err                =                              V            ref                    -                                                    R                5                                            R                4                                      ⁢                          (                              1                +                                  1                                                            sR                      5                                        ⁢                                          C                      2                                                                                  )                        ⁢                          (                                                V                  in                                -                                  V                  ref                                            )                                                          [                  FORMULA          ⁢                                          ⁢          1                ]            
Patent Document 1 proposes an error amplifier in which a resistor and a capacitor are connected as phase compensators, between an output terminal and an inverting input terminal.    [Patent Document 1] Japanese Published Patent Application No. 2006-238062